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An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect

Received: 2 March 2015     Accepted: 19 March 2015     Published: 2 April 2015
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Abstract

In this paper, we report an ultra-low power successive-approximation-register (SAR) analog-to digital converter (ADC) by using a DAC timing strategy with considering overshoot effect to increase the sampling rate. This ADC is simulated for power supplies voltage of 0.6 V and 1.2 V in a 130-nm CMOS technology. The results indicate an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM=5.3 to 9.3 fJ/conv-step.

Published in Journal of Electrical and Electronic Engineering (Volume 3, Issue 2)
DOI 10.11648/j.jeee.20150302.12
Page(s) 19-24
Creative Commons

This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.

Copyright

Copyright © The Author(s), 2015. Published by Science Publishing Group

Keywords

Data Converter, Overshoot Effect, Asynchronous Process, Power Efficiency, DAC Timing Strategy, Low Power Designs

References
[1] C.C. Liu, S.J. Chang, G.Y. Huang and Y.Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure ˮ, in IEEE J. Solid-State Circuits, vol.45, pp.731 - 740, April 2010.
[2] H. Wei, et al., “A 0.024 mm2 8b 400 MS/s SAR ADC with 2 b/cycle and resistive DAC in 65 nm CMOS ”, in IEEE ISSCC Dig. Tech. Papers, pp. 188-190, Feb. 2011.
[3] Y.M. Greshishchev, et al., “A 40 GS/s 6 b ADC in 65 nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, pp.390-391, Feb. 2010.
[4] A. Arian, M. Saberi, R. Lotfi, S. Hosseini-Khayat and Y. Leblebici, “A 10-bit 50-MS/s SAR ADC with split capacitive-array DAC”, Analog Integrated Circuits and Signal Processing, vol. 71, 583-589, Dec. 2011.
[5] Z. Cao, S. Yan, and Y. Li, “A 32 mW 1.25 GS/s 6 b 2 b/step SAR ADC in 0.13 m CMOS ” , in IEEE ISSCC Dig. Tech. Papers, pp.542–543, Feb. 2008.
[6] P. Schvan, et al., “A 24 GS/s 6 b ADC in 90 nm CMOS”, in IEEE ISSCC Dig. Tech. Papers, pp.544–634, Feb. 2008.
[7] S.W.M. Chen and R.W. Brodersen, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-µm CMOS”, in IEEE J. Solid-State Circuits, vol. 41, pp.2669-2680, Dec. 2006.
[8] J. Yang, T.L. Naing and R.W. Brodersen, “A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing”, in IEEE J. Solid-State Circuits, vol. 45, pp.1469-1478, Aug. 2010.
[9] Z. Huang, et al., “Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies”, in IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, vol.29, pp. 250-260, Feb. 2010.
[10] R. Sekimoto, A. Shikata, T. Kuroda and H. Ishikuro, “A40nm50S/s–8MS/sultralowvoltageSARADCwithtimingoptimizedasynchronousclockgenerator”, in Proc. ESSCIRC, pp.471-474, Sept. 2011.
[11] J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, 2nd ed., Prentice Hall: New Jersey, 2003, pp. 177-190.
[12] I.S. Jung, M. Onabajo and Y.B. Kim, “A 10-bit 64 MS/s SAR ADC using variable clock period method”, in IEEE International Midwest Symp. Circuits Syst, pp. 1144-1147, Aug. 2013.
[13] A. Shikata, R. Sekimoto, T. Kuroda and H. Ishikuro, “A 0.5 V 1.1MS/sec 6.3fJ/Conversion-Step SAR-ADC with Tri-Level Comparator in 40 nm CMOS,”, in IEEE J. Solid-State Circuits, vol. 47, pp. 1022-1030, April 2012.
[14] P. Harpe, Y. Zhang, G. Dolmans, K. Philips and H. de Groot, “A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to -16fJ/conversion-step,” IEEE ISSCC Dig. Tech. Papers, pp. 472-474, Feb. 2012.
Cite This Article
  • APA Style

    M. Dashtbayazi, M. Sabaghi, S. Marjani. (2015). An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect. Journal of Electrical and Electronic Engineering, 3(2), 19-24. https://doi.org/10.11648/j.jeee.20150302.12

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    ACS Style

    M. Dashtbayazi; M. Sabaghi; S. Marjani. An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect. J. Electr. Electron. Eng. 2015, 3(2), 19-24. doi: 10.11648/j.jeee.20150302.12

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    AMA Style

    M. Dashtbayazi, M. Sabaghi, S. Marjani. An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect. J Electr Electron Eng. 2015;3(2):19-24. doi: 10.11648/j.jeee.20150302.12

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  • @article{10.11648/j.jeee.20150302.12,
      author = {M. Dashtbayazi and M. Sabaghi and S. Marjani},
      title = {An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect},
      journal = {Journal of Electrical and Electronic Engineering},
      volume = {3},
      number = {2},
      pages = {19-24},
      doi = {10.11648/j.jeee.20150302.12},
      url = {https://doi.org/10.11648/j.jeee.20150302.12},
      eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20150302.12},
      abstract = {In this paper, we report an ultra-low power successive-approximation-register (SAR) analog-to digital converter (ADC) by using a DAC timing strategy with considering overshoot effect to increase the sampling rate. This ADC is simulated for power supplies voltage of 0.6 V and 1.2 V in a 130-nm CMOS technology. The results indicate an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM=5.3 to 9.3 fJ/conv-step.},
     year = {2015}
    }
    

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    T1  - An Optimized DAC Timing Strategy in SAR ADC with Considering the Overshoot Effect
    AU  - M. Dashtbayazi
    AU  - M. Sabaghi
    AU  - S. Marjani
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    DO  - 10.11648/j.jeee.20150302.12
    T2  - Journal of Electrical and Electronic Engineering
    JF  - Journal of Electrical and Electronic Engineering
    JO  - Journal of Electrical and Electronic Engineering
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    EP  - 24
    PB  - Science Publishing Group
    SN  - 2329-1605
    UR  - https://doi.org/10.11648/j.jeee.20150302.12
    AB  - In this paper, we report an ultra-low power successive-approximation-register (SAR) analog-to digital converter (ADC) by using a DAC timing strategy with considering overshoot effect to increase the sampling rate. This ADC is simulated for power supplies voltage of 0.6 V and 1.2 V in a 130-nm CMOS technology. The results indicate an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM=5.3 to 9.3 fJ/conv-step.
    VL  - 3
    IS  - 2
    ER  - 

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Author Information
  • Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran

  • Laser and Optics Research School, Nuclear Science and Technology Research Institute (NSTRI), Tehran, Iran

  • Department of Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran

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